Since the release of the "White Paper on the Industrialization of Carbon Nanotube Wafers", we have received many inquiries from friends. These questions range from materials, applications, to industrialization, with varying focuses, yet all revolve around the same core:

Where have carbon nanotube wafers gone?

This Q&A compiles 18 of the most representative questions, covering technical principles, process routes, and industry landscapes, with the hope of providing some reference for partners who are interested in this field.

The content is based on the public information from the "White Paper on Carbon Nanotube Wafer Industrialization" by Enlighten Semiconductor. The full text can be found at the end of the article, and the complete technical details are subject to the official disclosure in the white paper.

01 What is Xinjing doing (positioning and products)

Q1 What is a carbon nanotube wafer?

A: It refers to CNT mesh films or array films prepared on substrates such as silicon oxide, silicon nitride, glass, and quartz, delivered in a "wafer form" to facilitate subsequent semiconductor processing steps. (See pages 14-15 of the white paper for details)

Q2 Does Xinjing specialize in materials, process packages, or chips?

A：Focusing on Focusing on "carbon nanotube wafers + device process solutions", we provide material and process enabling technologies. In the medium and long term, we aim to collaborate with industry partners to advance device/chip and system applications. (p11, p14–p17, p23)

Q3 What is the difference between network wafers (NW) and array wafers (AW)?

A: NW is more inclined to "network-like thin films" with adjustable density (10-50 fibers/um), suitable for RF switches/sensing; AW emphasizes "directional high-density arrays" (100-300 fibers/um), more oriented towards high-end RF and integrated circuit research and development. (p14–p15)

Q4. Are the carbon nanotube wafers from Xinjing and the carbon nanotubes commonly used in lithium batteries made from the same material? What are the differences? Are the carbon nanotube raw materials prepared in-house by the company?

A: Although they are both called carbon nanotubes, they are targeted at completely different industries and exhibit vastly different properties and morphologies.

1. Different purposes: conductive additives vs semiconductor channel materials

· Carbon nanotubes in lithium-ion batteries are primarily used as conductive network additives, with the core objective of "enhancing the conductivity, improving the cycling durability, and controlling the cost of the electrode.".

·Carbon Semiconductor's carbon nanotube wafers are targeted at chip devices, with the core pursuit being "stable electron transport as a channel material within transistors". The goal is to achieve controllable electrical properties and manufacturability. (For the overall positioning of the white paper, see p11, and for the products, see p14–p17)

2. Different electrical requirements: mixed conductivity is sufficient vs. a high proportion of semiconductivity is necessary

·Lithium battery applications usually do not require "must be semiconductor type". In many cases, the mixture of metallic and semiconducting properties does not pose a problem, and may even be more conducive to conductivity.

·For transistors, the opposite is true: a high proportion of semiconducting carbon nanotubes is needed to minimize the risk of leakage and short circuits. The white paper emphasizes the "semiconductor purity/semiconducting proportion" indicator (such as >99.9999% or higher) for this reason. (p12, p18, p19, p23)

3. Different forms and delivery methods: powder/slurry vs wafer-level thin film/array

·The common delivery forms of lithium-ion batteries are powder, dispersion liquid, or slurry, with focus on dispersibility, conductive network formation ability, and cost

·Xenogenix delivers wafer-level network/array thin films (NW/AW, etc.), emphasizing wafer size, uniformity, controllable density, and compatibility with subsequent semiconductor processes. (p14–p15, p18)

4. Different manufacturing standards: electrochemical system vs semiconductor cleanliness and pollution control system

·Semiconductor processes have stricter requirements for impurities, metal contamination, repeatability, reliability verification, etc. Materials and processes must be able to enter the Fab process and be stably reproduced. (p8, p17, p20–p21, p33)

Q5 Why is the emphasis on 8 inches?

A: It is more aligned with commonly used industrial dimensions, facilitating integration with existing equipment and processes, and reducing the barriers to entry. The white paper reveals that an 8-inch pilot production line has been established and is capable of mass supply. (p9, p18, p24)

Q6 Why develop a 12-inch product?

A: 12-inch is closer to mainstream Si-based advanced production lines: once the materials and processes are mature, it is more conducive to large-scale introduction, improving production efficiency and reducing unit costs, and it also better meets the requirements of high-end applications for consistency and supply capability. Xinjing is carrying out forward-looking research and development and verification of 12-inch while promoting the engineering of 8-inch. (p9, p14, p24)

Why does 02 Vinyl Crystal make CNT wafers (industry background and rational understanding)

Q7 Should  carbon nanotubes immediately replace silicon?

A: No, it's not. Carbon nanotubes and silicon are not a "zero sum game", a more practical path is "silicon carbon synergy, complementary advantages". We believe that the development of carbon based technology will go through two stages:

● Incremental market entry: By utilizing the low-temperature process and high-frequency characteristics of carbon nanotubes, we will first enter the more easily imported characteristic processes (such as high-performance RF, uncooled infrared) and the later integration (3D interconnection, on-chip storage) that silicon-based chips cannot achieve, as a "super level plug-in" for silicon-based chips.

● Core computing power iteration: As the process maturity increases, gradually undertake core computing tasks in advanced process logic chips (such as nodes below 1nm).

Regarding ecological compatibility, we can use the analogy of a "central kitchen": a semiconductor wafer fab is like an expensive "precision central kitchen"; Lithography machines, etching machines, and other equipment are extremely expensive "cooking utensils"; Silicon has been the "main material" in this kitchen for the past sixty years.

The carbon based wafers made by Enjing do not essentially require a kitchen overhaul, but instead bring a high-end "new ingredient". Cooks (engineers) can still use existing stoves and cookware (mature lithography and etching equipment) by adjusting the heat and recipe (process recipe) to create a high-performance "top-level dish" (carbon based chip).

This means that carbon based technology maximizes the reuse of trillions of equipment assets accumulated by humans in the silicon-based era, which is the economic foundation for its industrialization. （p7、p17、p31–p33）

Q8 Why does  emphasize Fab compatible CMOS processes?

A: The difference between "materials made" and "being able to stably produce chips in the factory" is often the process system. The lift off route commonly used in many laboratories is more suitable for making prototype samples, but once it moves towards wafer level and batch manufacturing, it is easy to encounter several types of hard problems:

Difficulty in ensuring yield and consistency: photoresist residue, metal edge burrs/fractures, pattern size fluctuations, and insufficient cross chip uniformity can widen the distribution of device parameters, making it difficult for yield to steadily climb.

Poor scalability: The laboratory can produce results that look good at a certain point/piece, but scaling up to 8 inches or 12 inches and achieving batch stability will be challenged by process windows, equipment repeatability, and statistical tail defects.

Not matching the production line specifications: Fab prefers the standard "photolithography etching deposition CMP cleaning detection" process, which facilitates pollution control, online monitoring, reliability verification, and quality system operation; Lift off is more difficult to meet these specifications on many modules.

Ultimately, it needs to be integrated with the silicon ecosystem: whether it's RF, 3D integration, or specialty devices, many of them require integration into existing production lines and collaboration with silicon-based circuits/downstream processes. Fab compatible processes can significantly reduce the cost and validation cycle of partner imports.

Therefore, emphasizing the "Fab compatible CNT CMOS process" is essentially a key step in solving the transition from "laboratory feasible" to "industrial manufacturable": standardizing processes, improving yield, improving reliability, and truly integrating into the existing semiconductor manufacturing ecosystem. (See p8, p17, p21, p33 for relevant statements in the white paper)

Q9 The white paper states that 'materials determine the upper limit', what are the advantages of CNT?

A: Carbon nanotube materials themselves have material characteristics such as ultra-thin structure, potential high mobility, and low parasitism. As the channel size of silicon-based devices continues to shrink, the interface scattering on rough surfaces severely restricts the transport characteristics of charge carriers. Carbon nanotubes with a thickness of 1nm and a smooth surface naturally have the characteristic of low interface scattering and are considered as one of the important candidate directions for advanced node channel materials. （p6）

Q10 Can you explain in plain language why it is possible to achieve silicon based 10nm performance using only 28nm process based on carbon nanotube wafers?

A: Both carbon nanotubes and silicon in chips are essentially doing the same thing: acting as "channel materials" that allow electrons to run from the source to the drain. We can use "road transport capacity" as an analogy:

Think of channels as roads and electronics as vehicles. One important aspect of chip performance is how many vehicles can be driven per unit time (current/switch speed), as well as how much fuel is required to drive (power consumption).

Carbon nanotubes are more like "specialized highways that are smoother, straighter, and have higher speed limits". Carbon nanotubes are naturally one-dimensional, very "thin" channels (with a diameter of about 1 nm), and electrons inside are more like walking on a "dedicated fast lane", less likely to be disturbed by collisions, running faster overall, and braking more flexibly (corresponding to better electrical transport potential, stronger electrostatic control, and lower parasitic problems).

Silicon is more like a 'wider but more congested, lower speed ordinary road'. Silicon is a bulk material, and the channel is more like a "multi lane ordinary road". Although it may appear "wider" (finer craftsmanship can make way for shorter and denser paths), electrons are more susceptible to various "congestion factors" caused by materials and structures (scattering, short channel effects, parasitic capacitance/resistance, etc.), so to achieve the same traffic efficiency, it is often necessary to make the "road system" finer and more expensive (more advanced nodes and more complex structures).

So the intuitive meaning of "28nm CNT may benchmark against 10nm silicon" is: the same requirement is to "reach the same destination in 1 hour (with the same performance goal)": on the "high-speed dedicated lane" of carbon nanotubes, with the relatively mature construction level of 28nm, it is also possible to run; On the "ordinary road" of silicon, it is often necessary to repair the road to a finer level (achieving a more advanced and expensive construction level of 10nm) in order to have a better chance of running.

Q11 What does  mean 'semiconductor purity>99.99999%'?

A: Mainly refers to the high proportion of semiconducting CNTs, which is an important foundation for device/circuit manufacturing; The white paper presents the key technological routes for purification and wafer fabrication. (p19; see p12, p18, p23 for indicator description)

Where can 03 carbon nanotube crystal circles be used (application prospects)

Q12 Why is CNT capacitance/decoupling related to AI?

A: The higher the computing power of AI, the more afraid it is of power supply "shaking"; Decoupling capacitors are the "buffer" for voltage regulation. If CNT capacitors can demonstrate advantages in high frequency and integration methods, it may directly improve the stability and energy efficiency upper limit of high computing power systems. The VACNT structure is expected to be compatible with downstream integration, making capacitors closer to the chip and more compact (p29)

Q13 What does CNT infrared imaging need to solve?

A: The white paper cites publicly available information and believes that CNT has potential in material coefficients and other aspects, and is expected to be used for more compact, lower power consumption, or lower cost uncooled infrared solutions. （p30）

Q14 Why is  CNT RF worth paying attention to?

A: The white paper emphasizes the potential of CNT devices in high frequency and low power consumption, as well as in the direction of "silicon-based digital+CNT RF" heterogeneous integration, and discloses the phased progress in RF direction. （p31、p25）

Q15 What is  M3D (Single Chip 3D)?

A: Stacking different functional layers vertically on a single chip can improve integration and energy efficiency compared to existing packaging technologies; The white paper regards it as an important architectural direction for the post Moore era. （p32）

04 Other Frequently Asked Hard Questions (How to Determine 'True Progress')

Q16 indicator is strong ≠ energy production, what is the difference in the middle?

A: Poor in wafer level consistency, repeatable processing, quality system, and cost; The white paper provides a climbing path of "technological breakthrough → process solidification → mass production". （p24）

Q17 Why didn't you provide the full name and details for "customer verification/tape out" ?

A: The semiconductor industry chain is usually subject to strict confidentiality constraints. The white paper discloses the progress facts through stage milestones and anonymous customer statements. （p25、p35）

Q18 As an external observer, what signals should be focused on to determine whether progress is reliable?

A: Focus on three dimensions of signals: stable delivery (able to sustain supply), reproducible processing (able to repeatedly enter the process), and multi-party collaborative verification (not just a single device, single point demonstration). （p20–p25、p33）

This material is only used for science popularization and information communication, and does not constitute investment advice, offer or commitment; There is uncertainty in forward-looking statements, and the specific information shall be subject to the official disclosure of the company and the actual progress of the project. (Refer to White Paper p35)